1. Field of the Invention
The present invention relates to a method for fabricating buried bit lines, and more particularly, the present invention relates a method for fabricating buried bit lines of a mask ROM.
2. Description of the Prior Art
A read-only memory (ROM) is a nonvolatile memory where information is permanently stored through the use of custom masks during fabrication. Mask ROMs with buried bit lines (flat cell) are the most popular types of ROM. Conventionally, the buried bit lines are formed by doping impurities into the substrate through a bit line mask.A high-dosage ion implantation process is used to reduce the buried bit line sheet resistance. When the integration increases, i.e. a smaller device size, the buried bit line width, namely the channel critical dimension (CD) also shrinks. Therefore, when the wafer is subjected to high temperature conditions in subsequent processing steps, the doping impurities within the buried bit lines will diffuse outwards and towards one another causing punch-through to take place between adjacent buried bit lines.
In order to prevent punch-through phenomenon between adjacent buried bit lines, a conventional cell punch through (CPT) ion implantation process through a CPT mask is performed to isolate the adjacent buried bit lines and to prevent the diffusion of impurities from the buried bit lines. FIG. 1 to FIG. 2 are schematic diagrams of a conventional method for fabricating buried bit lines 20 of a mask ROM. Referring to FIG. 1, a semiconductor substrate 10 comprising a P-type well 12 is provided. First, the surface of the semiconductor substrate 10 is thermally oxidized to form a pad oxide layer 14 with a thickness between 125 and 250 angstroms (xc3x85). A photoresist layer (not shown) is coated on the pad oxide layer 14 and patterned as is conventional in the art to form a photoresist mask 16 having openings where buried bit lines 20 are to be formed within the semiconductor substrate 10. An ion implantation process 18 is performed through the photoresist mask 16. Typically, arsenic (As) ions are implanted at a dosage of between 1.5xc3x971015 and 3xc3x971015 atoms/cm2, and an energy between 40 and 80 KeV to form the buried bit lines 20 within areas of the P-type well 12 which are not shielded by the photoresist mask 16.
Referring to FIG. 2, a CPT halo implantation process 22 is performed through the photoresist mask 16 to form halo regions 24 within the P-type well 12 encompassing the buried bit lines 20. A typical CPT halo ion implantation process 22 implants boron (B) ions at a dosage between 1.2xc3x971013 and 1.5xc3x971013 atoms/cm2, and an energy between 100 and 140 KeV. This results in longer lateral diffusion areas 24, which encompass the buried bit lines 20 and are used to isolate the adjacent buried bit lines 20.
The conventional CRT halo ion implantation process 22 is utilized to form the halo regions 24, encompassing the buried bit lines 20 for reducing punch-through phenomenon between the adjacent buried bit lines 20. However, when the mask ROM dimension shrinks, the buried bit line width also shrinks and the buried bit line sheet resistance increases. In addition, the punch-through voltage between the adjacent buried bit lines becomes unacceptably low. Therefore, the high-dosage and the CPT halo ion implantation process 22 are not suitable for preventing punch-through phenomenon between the adjacent buried bit lines 20.
Another method for forming a lightly doped drain (LDD) by utilizing a spacer as a mask is used to prevent punch-through phenomenon. FIG. 3 to FIG. 4 are schematic diagrams depicting a conventional method for fabricating buried bit lines of a mask ROM. Referring to FIG. 3, a semiconductor substrate 30 comprising a P-type well 32 is provided, and a pad oxide layer 34 is formed on the P-type well 32. A patterned photoresist layer 36 is coated on the pad oxide layer 34 to define patterns of buried bit lines (not shown), and then a polysilicon layer 38 is uniformly formed over the semiconductor substrate 30 to fill spaces between the patterned photoresist layer 36.
Referring to FIG. 4, an etching back process is performed to remove portions of the polysilicon layer 36, forming a spacer 40 on a sidewall of the patterned photoresist layer 36. An ion implantation process 42 implants phosphorous (P) ions at a dosage of approximately 1xc3x971015 atoms/cm2, and an energy between 50 and 100 KeV to form an N+-type doped region 44 within the areas on P-type well 32 which are not shielded by the patterned photoresist layer 36 and the spacer 40. In addition, an N-type doped region 46 is formed within the P-type well 32 beneath the spacer 40. The spacer 40 blocks some of the implanted P ions, therefore the doped region 46 becomes Nxe2x88x92. The N+-type doped region 44 and the N-type doped region 46 constitute the buried bit lines of the mask ROM.
In the conventional method, the low-dosage N-doped region positioned at two sides of the buried bit lines formed by utilizing the spacer as the mask are used to prevent punch-through phenomenon between the adjacent buried bit lines. When the bit line width shrinks, the method for fabricating a suitable width spacer between the buried bit line with small channel CD is a main concern in the high-integration semiconductor process. In addition, a conventional pocket ion implantation process is utilized to form a pocket-doped region surrounding the buried bit lines. However, a large tilt-angle ion implantation process is utilized in the smaller bit line width and the thicker photoresist layer.
It is therefore an objective of the present invention to provide a method for fabricating buried bit lines of a mask ROM for reducing electric field strength of the buried bit lines and preventing punch-through phenomenon between the adjacent buried bit lines.
A claimed embodiment of the present invention involves coating a semiconductor substrate with a photoresist layer. The photoresist layer is patterned to form a photoresist pattern with a first line width. A first ion implantation process is performed to form a doped region in the semiconductor substrate not covered by the photoresist pattern. The photoresist pattern is trimmed to shrink the first line width to a second line width by using a resist trimming process in order to expose a region of the semiconductor substrate next to the doped region. A second ion implantation process is performed to form a lightly doped drain (LDD) region in the region of the semiconductor substrate next to the doped region, thus the doped region and the LDD region constitute the buried bit lines of the mask ROM. Then the photoresist layer is stripped.
The present invention utilizes the buried bit lines composed of the doped region and the LDD region of the mask ROM for reducing the buried bit line electric field strength effectively and reducing hot carrier effect. The LDD region positioned at two sides of the buried bit lines increases the punch-through voltage and prevents punch-through phenomenon between the adjacent buried bit lines. In the present invention, a wider channel critical dimension (CD) of the buried bit line is formed, and then a resist trimming process is performed to shrink the channel CD to a demanded critical CD of the semiconductor process. Therefore, the present invention is not limited to smaller devices and is suitable for using in a high-integration semiconductor process or in a high-density memory.